LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--MULTIPLEX 2 INPUTS

ENTITY ic_7 IS

    PORT(clear, pin1, pin2, pin3, pin4, pin5, pin6, pin10, pin11, pin12, pin13, pin14, pin15 : IN STD_LOGIC := '0'; 
        pin7, pin9: OUT STD_LOGIC  := '0');

END ic_7;

ARCHITECTURE mux2_ic OF ic_7 IS

SIGNAL MUX: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";

BEGIN

    MUX(0) <= pin14;
    MUX(1) <= pin2;

    PROCESS(MUX, pin1, pin3, pin4, pin5, pin6, clear)
    BEGIN
        IF(pin1 = '1' OR clear = '1')THEN
            pin7 <= '0';
        ELSIF(MUX = "00")THEN
            pin7 <= pin6;
        ELSIF(MUX = "01")THEN
            pin7 <= pin5;
        ELSIF(MUX = "10")THEN
            pin7 <= pin4;
        ELSIF(MUX = "11")THEN
            pin7 <= pin3;
        ELSE
            pin7 <= '0';
        END IF;
    END PROCESS;
	 
    PROCESS(MUX, pin15, pin10, pin11, pin12, pin13, clear)
    BEGIN
        IF(pin15 = '1' OR clear = '1')THEN
            pin9 <= '0';
        ELSIF(MUX = "00")THEN
            pin9 <= pin10;
        ELSIF(MUX = "01")THEN
            pin9 <= pin11;
        ELSIF(MUX = "10")THEN
            pin9 <= pin12;
        ELSIF(MUX = "11")THEN
            pin9 <= pin13;
        ELSE
            pin9 <= '0';
        END IF;
    END PROCESS;

END mux2_ic;